1. Field of the Invention
The present invention is related to processing systems and processors, and more specifically to a pipelined processor core with dynamic instruction stream mapping.
2. Description of Related Art
In present-day processor cores, pipelines are used to execute multiple hardware threads corresponding to multiple instruction streams, so that more efficient use of processor resources can be provided through resource sharing and by allowing execution to proceed even while one or more hardware threads are waiting on an event.
In existing systems, specific resources and pipelines are typically allocated for execution of the different instruction streams and multiple pipelines allow program execution to continue even during conditions when a pipeline is busy. However, resources are still tied up for pipelines that are busy, and when all the pipeline(s) assigned to an instruction stream are busy, the instruction stream is stalled, reducing the potential throughput of the processor core.
It would therefore be desirable to provide a method for processing program instructions that provides improved flexibility and throughput.